1. Field of the Invention
The present invention generally relates to fabrication of a semiconductor memory device, and more particularly, to a fabrication process of a semiconductor memory device having a cylinder-type stacked capacitor and to a semiconductor memory device fabricated by such a process.
2. Description of the Related Art
Along with a continuous trend toward increasing the capacities of memory devices, such as a DRAM or an FeRAM, the charge-storage structure has been shifting from a MIS (metal-insulator-semiconductor) structure to a MIM (metal-insulator-metal) structure, which is capable of achieving a larger capacitance. Various studies has also been made for dielectric materials of a cell capacitor, and it has been proposed to use high-dielectric constant materials, such as tantalum pentoxide and barium strontium titanate (BST:BaxSr1-xTiO3), or ferroelectric materials, such as lead zirconium titanate (PZT:PbZrxTi1-xO3) and strontium bismuth tantalite (SBT:SrBa2Ta2O9). When employing such a high dielectric material or a ferroelectric material, non-oxidizing conductive metals or conductive oxides are selected for the storage electrode, from the viewpoint of preventing peeling and leakage.
For example, ruthenium (Ru), iridium (Ir), and platinum (Pt), which belong to the platinum group, are used in the storage electrode because of their non-oxidizing characteristic. Conductive oxides, such as RuO2 or IrO2, and conductors with a perovskite structure, such as SrRuO, may also be used. To fabricate a storage electrode using these materials, a conductive layer is formed by physical film deposition, such as sputtering or vacuum evaporation, and the layer is subjected to a thermal process for the purposes of improving the adhesion, reducing hillocks and pin holes, and roughing the surface, as disclosed in JPA 7-297364, JPA 8-335679, and JPA 8-340091.
In general, it is difficult to process a metal of the platinum group, and particular techniques, such as CMP and dry etch, are required. In addition, the platinum-group metals are not so good in adhesion with electrically insulating materials. For this reason, a glue layer (which also referred to as a “barrier metal”) made of, for example, titanium nitride (TiN) or tungsten nitride (WN), is inserted between the electrode layer and an interlevel dielectric (or an insulating layer) to improve the adhesion between them.
However, the glue layer comprising a refractory metal easily oxidizes upon touching an oxygen-containing high-dielectric constant material, such as tantalum penoxide or barium strontium titanate (BST). Oxidation of the glue layer may produce a leakage path, or cause peeling, and consequently, the electric characteristics of the device are adversely affected. To avoid such electrically adverse influence, some countermeasure has to be taken prior to forming an oxygen-containing high-dielectric constant film of a cell capacitor, so as to prevent the glue layer (or the barrier metal) from directly touching the dielectric material having a high dielectric constant. For instance, in the fabrication process of a cylinder-type stacked capacitor, the glue layer (or the barrier metal) is removed by a wet process prior to forming a high-dielectric constant film.
FIGS. 1A through 1L illustrate a conventional fabrication process of a cylinder-type stacked capacitor. Brief explanation will be made of the conventional fabrication process. Prior to forming a cell capacitor (i.e., a charge storage capacitor), tungsten (W) plug 117 protected by a titanium nitride (TiN) layer 121 is formed between the bit lines 115, as illustrated in FIG. 1A. The plug 117 electrically connects the cell capacitor to an underlying access transistor (not shown). Then, a support layer 123 and a base 122 are successively formed, as illustrated in FIG. 1B. Then, a silicon dioxide (SiO2) interlevel dielectric 125 is formed over the base 122, as illustrated in FIG. 1C. A hole 124 for accommodating a storage node is formed by etching the SiO2 interlevel dielectric 125, the base 122, and the support layer 123 until the plug 117 is exposed, as illustrated in FIG. 1D.
Then, a titanium nitride (TiN) glue layer 127 and a bottom electrode layer 129 are successively formed inside the hole 124, as illustrated in FIG. 1E and FIG. 1F. The bottom electrode layer 129 is made of a metal of the platinum group, for example, ruthenium (Ru). The hole is filled with a resist material 131, as illustrated in FIG. 1G.
The surface is planarized until the SiO2 interlevel dielectric 125 is exposed, as illustrated in FIG. 1H. In this planarization, the bottom electrode layer 129 positioned over the top of the SiO2 interlevel dielectric 125 is removed by chemical mechanical polishing (CMP) to isolate adjacent cell capacitors, and then, TiN glue layer 127 positioned on the top of the SiO2 interlevel dielectric 125 is removed by reactive ion etching (RIE). Then, the SiO2 interlevel dielectric 125 is removed by wet etching using BHF, and the resist 131 filled in the hole is removed by stripping (or “ashing”), as illustrated in FIG. 1I and FIG. 1J, respectively. At this point of time, the TiN glue layer 127 and the bottom electrode layer 129, which are shaped into a cylinder shell, are left.
As has been described above, if an oxygen-containing high-dielectric constant film or an oxidic ferroelectric film is formed directly over the glue layer 127 of a refractory metal, such as titanium nitride (TiN), the glue layer 127 is oxidized easily. Accordingly, the glue layer 127 is removed by a wet process prior to forming a dielectric layer of the capacitor, as illustrated in FIG. 1K. Then, a tantalum oxide (TaO) dielectric layer 135 is formed directly on the bottom electrode layer 129 that defines a cylinder shell, and subsequently, a top electrode layer 137 is formed over the TaO dielectric layer 135 using a metal of the platinum group, such as ruthenium (Ru), as illustrated in FIG. 1L. In this manner, the conventional cylinder-type stacked capacitor is completed.
With the conventional fabrication process, a gap or a groove 133 is produced around the cylinder shell, between the base 122 and the bottom electrode layer 129 near the surface of the base 122, during the removal of the TiN glue layer 127, as illustrated in FIG. 1K. The gap 133 becomes a serious problem because the base 122 for supporting the cylinder shell of the bottom electrode layer 129 becomes unstable. Such instability may cause the cylinder shell to fall down, or at the worst, the cylinder itself may become separated from the base 122 during the wet process.
Furthermore, if there are pin holes in the bottom electrode layer 129, the TiN glue layer 127 positioned on the top face of the plug 117 may melt during the wet process, which results in the tungsten (W) plug 117 being lost due to the cell effect.
After all, the glue layer (or the barrier metal) 127 formed for the purpose of improving the adhesion between the bottom electrode film 129 of a platinum-group metal and the SiO2 interlevel dielectric 125 has to be removed in order to prevent leakage current due to omission of oxygen from the dielectric layer of the cell capacitor, in spite of the above-described problems. Consequently, the fabrication process becomes complicated with the increased number of fabrication steps and the increased fabrication cost.
Still another problem is difficulty of cell isolation because a portion of the bottom electrode layer 129 comprising a platinum-group metal has to be processed using a CMP method.